Basic Electrical Engineering

We have already gain understandings of nodes, branches and loops. German physicist Gustav Robert Kirchhoff gave two laws which alongside with Ohm’s laws give us a powerful tool of circuit analysis.

Kirchhoff’s Current Law (KCL):

Kirchhoff stated that, amount of current entering or leaving a node should be equal. That means the algebraic sum of currents with respect to a node should always be zero.

A water pipe analogy would make it easier for us to understand this law. Suppose in a network of water pipes, water comes and leaves through different branches. At a single point of this network the amount of water coming to that node or point from different branch is always equal to the amount of water leaving from that point or node. If we think water as current then the amount of current coming through different branches at a node in a circuit must be equal to the amount of current leaving that node. This is Kirchoff’s Current Law (KCL).

To illustrate KCL look at the figure below:

 

At figure A, current I is entering node X and I1 and I2 is leaving node X. And at node Y, I1 and I2 is entering node Y and I is leaving node Y.

Hence, according to KCL:   

I=I1+I2=I-I1-I2 = 0

Here current I1 and I2 has opposite polarity of I. So we can express it as: I+I1+I2=0

At figure B, same thing happens. Current I1 and I2 are entering node Z and I3, I4 and I5 is leaving node Z.

Hence, according to KCL:

I1+I2+I3+I4+I5=0

Kirchoff’s Voltage Law (KVL):

The statement of KVL is: In a closed path or loop the algebraic sum all voltages must be zero. That means simply, the voltage sources will generate voltages and other elements will consume it. 

We already know the resistors have always a voltage drop, i.e they consume voltage. Other elements like capacitors and inductor also have voltage drops as they consume real or reactive power from the source. 

To illustrate KVL, let us see the figure below,

The voltage source E generates voltage or potential. Whereas Resistors have drops of E1, E2, E3 and E4. According to KVL, 

E = E1 + E2 + E3 +E4

As we can see from the figure, the signs of potential of resistors is opposite of voltage source. So,

E= -E1-E2-E3-E4

E+E1+E2+E3+E4=0

Hence, the algebraic sum of voltages in a loop is zero.